As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin FET). Fin FET devices typically include semiconductor fins with high aspect ratios and in which channel and source/drain regions of semiconductor transistor devices are formed. A gate is formed over and along the sides of the fin structure (e.g., wrapping) utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. In some devices, strained materials in source/drain (S/D) portions of the Fin FET utilizing, for example, silicon germanium (SiGe), silicon carbide (SiC), and/or silicon phosphide (SiP) may be used to enhance carrier mobility. For example, compressive stress applied to a channel of a PMOS device advantageously enhances hole mobility in the channel. Similarly, tensile stress applied to a channel of an NMOS device advantageously enhances electron mobility in the channel. However, there are challenges to the implementation of such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication.